Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Arrangement for the protection of three-dimensional structures on wafers

Arrangement for the protection of three-dimensional structures on wafers

US Patent 7514798 · Granted Apr 7, 2009

Estimated economic value: $184,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Process for producing layer structures for signal distribution2008
Method for producing a rewiring printed circuit board2008
Electronic component with compliant elevations having electrical contact areas a2008
Method for forming three-dimensional structures on a substrate2008
Method for improving the mechanical properties of BOC module arrangements2008
Process for producing metallic interconnects and contact surfaces on electronic 2007
Arrangement and process for protecting fuses/anti-fuses2007
Method for fabricating metallic interconnects on electronic components2007
Connection between a semiconductor chip and an external conductor structure and 2007
Method for protecting the redistribution layer on wafers/chips2006
Area efficient stacking of antifuses in semiconductor device2006
Manufacturing of a corrosion protected interconnect on a substrate2005