{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Innovated technique to reduce memory interface write mode SSN in FPGA", "item": "https://www.patentleaderboard.com/patent/7492185"}]}

Home › Innovated technique to reduce memory interface write mode SSN in FPGA

Innovated technique to reduce memory interface write mode SSN in FPGA

US Patent 7492185 · Granted Feb 17, 2009

Estimated economic value: $5,351,000 ⓘ

Assignee

Intel

Inventors

Joseph Huang (212 patents)
Chiakang Sung (194 patents)
Michael H. M. Chu (14 patents)
Yan Chong (90 patents)

View full patent text on Google Patents →