{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Method for implementing overlay-based modification of VLSI design layout", "item": "https://www.patentleaderboard.com/patent/7490308"}]}
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Home › Method for implementing overlay-based modification of VLSI design layout

Method for implementing overlay-based modification of VLSI design layout

US Patent 7490308 · Granted Feb 10, 2009

Estimated economic value: $5,620,000 ⓘ

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