Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Hierarchical scalable high resolution digital programmable delay circuit

Hierarchical scalable high resolution digital programmable delay circuit

US Patent 7456671 · Granted Nov 25, 2008

Estimated economic value: $6,627,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Backside self aligned skip via2025
Technique for enabling on-die noise measurement during ate testing and IST2025
Backside gate via structure using self-aligned scheme2025
Cell optimization through source resistance improvement2025
Generating a power delivery network based on the routing of signal wires within 2025
Providing deterministic frequency and voltage enhancements for a processor2025
Semiconductor device design mitigating latch-up2024
Hierarchical color decomposition of library cells with boundary-aware color sele2024
Dynamic guard band with timing protection and with performance protection2024
Dynamic guard band with timing protection and with performance protection2024
Region-based power grid generation through modification of an initial power grid2024
Hierarchical color decomposition of process layers with shape and orientation re2023