Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Error checking parity and syndrome of a block of data with relocated parity bits

Error checking parity and syndrome of a block of data with relocated parity bits

US Patent 7426678 · Granted Sep 16, 2008

Estimated economic value: $6,646,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Clocking architecture for communicating synchronous and asynchronous clock signa2025
Deterministic reset mechanism for asynchronous gearbox FIFOs for predictable lat2025
Systems and methods for imaging communication and control2024
Clocking architecture for communicating clock signals having different frequenci2024
Register integrity check in configurable devices2024
Distributed configuration of programmable devices2024
Compute dataflow architecture2023
Systems and methods for imaging communication and control2023
Compute dataflow architecture2022
Programmable device configuration memory system2022
Power delivery network for active-on-active stacked integrated circuits2022
Tracing status of a programmable device2022