Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Wafer stage storage structure speed testing

Wafer stage storage structure speed testing

US Patent 7417449 · Granted Aug 26, 2008

Estimated economic value: $4,862,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Staged bitline precharge2022
JTL-based superconducting logic arrays and FPGAS2020
Flexibile interfaces using through-silicon via technology2020
Memory system with signals on read lines not phase-aligned with Josephson transm2020
Configuration of multi-die modules with through-silicon vias2019
Error injection for assessment of error detection and correction techniques usin2019
JTL-based superconducting logic arrays and FPGAs2019
Swizzling in 3D stacked memory2019
Predictive multistage comparison for associative memory2018
Memory elements for performing an allocation operation and related methods2013
Method and apparatus to achieve more level thermal gradient2011
Multi-ported register cell with randomly accessible history2008