Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › High-speed serial link receiver with centrally controlled offset cancellation and method

High-speed serial link receiver with centrally controlled offset cancellation and method

US Patent 7391824 · Granted Jun 24, 2008

Estimated economic value: $20,489,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Coarse delay lock estimation for digital DLL circuits2021
Jitter cancellation with automatic performance adjustment2020
Digital phase control with programmable tracking slope having a programmable lin2020
Jitter cancellation with automatic performance adjustment2019
Coarse delay lock estimation for digital DLL circuits2019
Jitter cancellation with automatic performance adjustment2018
Phase detector in a delay locked loop2018
Dual-range clock duty cycle corrector2017
Digital phase control with programmable tracking slope2017
Glitch-free digitally controlled oscillator code update2017
XOR (exclusive or) based triangular mixing for digital phase control2016
Digital delay-locked loop (DLL) training2016