Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Reducing false error detection in a microprocessor by tracking instructions neutral to errors

Reducing false error detection in a microprocessor by tracking instructions neutral to errors

US Patent 7386756 · Granted Jun 10, 2008

Estimated economic value: $23,380,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Efficient neural network accelerator dataflows2025
Managing commit order for an external instruction relative to queued instruction2025
On-demand IP initialization within power states2025
Device and method for two-stage transitioning between reduced power states2025
Processor data cache with shared mid-level cache and low-level cache2025
Dynamic designation of instructions as sensitive for constraining instruction ex2025
Method and apparatus for managing power states2024
Managing power in an integrated circuit for high-speed activation2024
Technique for extended idle duration for display to improve power consumption2024
Semi-programmable and reconfigurable co-accelerator for a deep neural network wi2024
Device and method for efficient transitioning to and from reduced power state2024
Using a hardware-based controller for power state management2024