Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Repetitive erase verify technique for flash memory devices

Repetitive erase verify technique for flash memory devices

US Patent 7385851 · Granted Jun 10, 2008

Estimated economic value: $2,063,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

NAND memory cell string having a stacked select gate structure and process for f2021
NAND memory cell string having a stacked select gate structure and process for f2020
NAND memory cell string having a stacked select gate structure and process for f2020
NAND memory cell string having a stacked select gate structure and process for f2019
Programmable impedance memory device and related methods2019
NAND memory cell string having a stacked select gate structure and process for f2018
Resistive switching memory having a resistor, diode, and switch memory cell2016
Dual program state cycling algorithms for resistive switching memory device2016
Resistive switching memory device architecture for reduced cell damage during pr2016
Capacitor arrangements using a resistive switching memory cell structure2016
Barrier region underlying source/drain regions for dual-bit memory devices2015
Controlling AC disturbance while programming2013