Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Latch-based random access memory (LBRAM) tri-state banking architecture

Latch-based random access memory (LBRAM) tri-state banking architecture

US Patent 7266021 · Granted Sep 4, 2007

Estimated economic value: $24,410,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Latch-based random access memory2010
Enhanced power distribution in an integrated circuit2010
Enhanced power distribution in an integrated circuit2010
Flexible architecture component (FAC) for efficient data integration and informa2010
Web-enabled solutions for memory compilation to support pre-sales estimation of 2010
Web-enabled solutions for memory compilation to support pre-sales estimation of 2010
Generic methodology to support chip level integration of IP core instance constr2010
Generic methodology to support chip level integration of IP core instance constr2010
On-chip circuit for transition delay fault test pattern generation with launch o2009
Latch-based random access memory (LBRAM) with tri-state banking and contention a2007
Latch-based random access memory (LBRAM) with tri-state banking and contention a2007
Method and apparatus for high speed testing of latch based random access memory2007