Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7760578 | Enhanced power distribution in an integrated circuit | Michael N. Dillon, Bret Alan Oeltjen, Uday Anumalachetty, Thomas Antisseril | 2010-07-20 |
| 7720556 | Web-enabled solutions for memory compilation to support pre-sales estimation of memory size, performance and power data for memory components | Cristian T. Crisan, Ekambaram Balaji | 2010-05-18 |
| 7669155 | Generic methodology to support chip level integration of IP core instance constraints in integrated circuits | Balaji Ganesan, Ekambaram Balaji, Nicholas A. Oleksinski | 2010-02-23 |
| 7640461 | On-chip circuit for transition delay fault test pattern generation with launch off shift | Thai M. Nguyen, William Wu Shen, Christopher Coleman | 2009-12-29 |
| 7266021 | Latch-based random access memory (LBRAM) tri-state banking architecture | Bret Alan Oeltjen, Ekambaram Balaji | 2007-09-04 |
| 7233540 | Latch-based random access memory (LBRAM) with tri-state banking and contention avoidance | Bret Alan Oeltjen, Michael N. Dillon | 2007-06-19 |
| 7231563 | Method and apparatus for high speed testing of latch based random access memory | Ekambaram Balaji | 2007-06-12 |
| 7152194 | Method and circuit for scan testing latch based random access memory | Ekambaram Balaji, Giuseppe Fornaciari | 2006-12-19 |