Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for an efficient memory built-in self test architecture for high performance microprocessors

Method and apparatus for an efficient memory built-in self test architecture for high performance microprocessors

US Patent 7260759 · Granted Aug 21, 2007

Estimated economic value: $14,403,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method and apparatus for providing clock signals for a scan chain2019
Method and apparatus to control access to device enable features2013
Method and apparatus for testing memories with different read/write protocols us2007
Semiconductor device and method and apparatus for testing such a device2007
Method and apparatus for at-speed diagnostics of embedded memories2007
Method and apparatus for at-speed diagnostics of embedded memories2007
Architecture of an efficient at-speed programmable memory built-in self test2007
Programable multi-port memory BIST with compact microcode2007
Method and apparatus for testing multi-port memories2006
Method and system for monitoring and profiling an integrated circuit die tempera2006
Controller for monitoring temperature2005
Controller for monitoring temperature2005