{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Multilevel signal interface testing with binary test apparatus by emulation of multilevel signals", "item": "https://www.patentleaderboard.com/patent/7162672"}]}
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Home › Multilevel signal interface testing with binary test apparatus by emulation of multilevel signals

Multilevel signal interface testing with binary test apparatus by emulation of multilevel signals

US Patent 7162672 · Granted Jan 9, 2007

Estimated economic value: $9,900,000 ⓘ

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