Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and system for providing a power lateral PNP transistor using a buried power buss

Method and system for providing a power lateral PNP transistor using a buried power buss

US Patent 7098113 · Granted Aug 29, 2006

Estimated economic value: $8,461,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System for vertical DMOS with slots2012
System for vertical DMOS with slots2009
Method for providing a programmable electrostatic discharge (ESD) protection dev2009
Integrated device technology using a buried power buss for major device and circ2007
Method and system for providing a CMOS output stage utilizing a buried power bus2006
Method and system for vertical DMOS with slots2006
Method and system for a programmable electrostatic discharge (ESD) protection ci2006
Method of making truncated power enhanced drift lateral DMOS device with ground 2006
Buried power buss utilized as a ground strap for high current, high power semico2006
Integrated schottky diode using buried power buss structure and method for makin2006
Method of fabricating a bipolar transistor using selective epitaxially grown SiG2005
Buried power bus utilized as a sinker for high current, high power semiconductor2005