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Home › Method of generating an efficient stuck-at fault and transition delay fault truncated scan test pattern for an integrated circuit design

Method of generating an efficient stuck-at fault and transition delay fault truncated scan test pattern for an integrated circuit design

US Patent 7058909 · Granted Jun 6, 2006

Estimated economic value: $5,097,000 ⓘ

Assignee

Lsi

Inventors

Cam Luong Lu (3 patents)
Robert Brady Benware (20 patents)
Thai M. Nguyen (29 patents)

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