Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Single polisilicon emitter bipolar junction transistor processing technique using cumulative photo resist application and patterning

Single polisilicon emitter bipolar junction transistor processing technique using cumulative photo resist application and patterning

US Patent 7018778 · Granted Mar 28, 2006

Estimated economic value: $16,159,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Remotely reprovisioning a device to a new service provider by updating an embedd2017
Diagnostics of deployed devices based on network traffic2017
Method and apparatus for integrated circuit protection2016
Production of laterally diffused oxide semiconductor (LDMOS) device and a bipola2015
Production of high-performance passive devices using existing operations of a se2015
LDMOS device with double-sloped field plate2014
Use of plate oxide layers to increase bulk oxide thickness in semiconductor devi2014
Low on resistance CMOS “wave” transistor for integrated circuit applications2011
PN junction and MOS capacitor hybrid resurf transistor2011
Method for enhancing field oxide2010
PN junction and MOS capacitor hybrid RESURF transistor2010
Low on resistance CMOS transistor for integrated circuit applications2010