Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for scan testing and clocking dynamic domino circuits in VLSI systems using level sensitive latches and edge triggered flip flops

Method for scan testing and clocking dynamic domino circuits in VLSI systems using level sensitive latches and edge triggered flip flops

US Patent 7000164 · Granted Feb 14, 2006

Estimated economic value: $5,488,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Circuits and methods for routing crossbars with programmable vias2025
Automated flight operations system2022
Configuration or data caching for programmable logic device2022
Automated flight operations system2018
Partially depopulated interconnection arrays for packaged semiconductor devices 2017
Interposer with beyond reticle field conductor pads2017
ROM segmented bitline circuit2017
Semiconductor chip with thermal interface tape2017
Partially depopulated interconnection arrays for packaged semiconductor devices 2016
Fault tolerant scannable glitch latch2014
Microprocessor performance and power optimization through self calibrated induct2014
Integrated circuit package with input capacitance compensation2014