Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Gate-clocked domino circuits with reduced leakage current

Gate-clocked domino circuits with reduced leakage current

US Patent 6952118 · Granted Oct 4, 2005

Estimated economic value: $23,554,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Low standby leakage implementation for static random access memory2024
Low power content addressable memory2021
Method and apparatus to limit current-change induced voltage changes in a microc2010
Domino circuit with disable feature2009
Leakage control in integrated circuits2007
Word line transistor stacking for leakage control2005
Single stage pulsed domino circuit for driving cascaded skewed static logic circ2004
Method and apparatus for improving the performance of a floating point multiplie2004
Differential, low voltage swing reducer2004
Low power entry latch to interface static logic with dynamic logic2004
Low power entry latch to interface static logic with dynamic logic2004
Low power precharge scheme for memory bit lines2003