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Home › Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process

Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process

US Patent 6841831 · Granted Jan 11, 2005

Estimated economic value: $11,104,000 ⓘ

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