Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for eliminating false failures saved by redundant paths during circuit area analysis on an integrated circuit layout

Method for eliminating false failures saved by redundant paths during circuit area analysis on an integrated circuit layout

US Patent 6810510 · Granted Oct 26, 2004

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Low temperature process for diode termination of fully depleted high resistivity2022
Extracting comprehensive design guidance for in-line process control tools and m2016
Method and apparatus for determining fault sources for device failures2005
Method for avoiding false failures attributable to dummy interconnects during de2004
Method for avoiding false failures attributable to dummy interconnects during de2004
Correction of overlay offset between inspection layers2004
Method for selecting an optimal level of redundancy in the design of memories2004
Method for identifying the cause of yield loss in integrated circuit manufacture2004
Timing delay generator and method including compensation for environmental varia2000