Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9400865 | Extracting comprehensive design guidance for in-line process control tools and methods | Sagar A. Kekare | 2016-07-26 |
| 6810510 | Method for eliminating false failures saved by redundant paths during circuit area analysis on an integrated circuit layout | Julie Segal | 2004-10-26 |
| 6795953 | Method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design | Julie Segal | 2004-09-21 |