Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Apparatus and method for calculating temporal deterioration margin amount of LSI, and LSI inspection method

Apparatus and method for calculating temporal deterioration margin amount of LSI, and LSI inspection method

US Patent 6795802 · Granted Sep 21, 2004

Estimated economic value: $146,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Decoration method of printed matter and printed matter2019
Delay calculating method in semiconductor integrated circuit2011
Method of designing semiconductor integrated circuit, designing apparatus, semic2010
Semiconductor integrated circuit2009
Timing verification method for semiconductor integrated circuit2007
Apparatus for statistical LSI delay simulation2007
Operation analyzing method for semiconductor integrated circuit device, analyzin2007
Timing analysis method and apparatus2007
Method for setting design margin for LSI2007
Method for calculation of cell delay time and method for layout optimization of 2006
Method for designing semiconductor integrated circuit2006
Method and apparatus for designing semiconductor integrated circuit device based2005