Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7308381 | Timing verification method for semiconductor integrated circuit | — | 2007-12-11 |
| 7239997 | Apparatus for statistical LSI delay simulation | — | 2007-07-03 |
| 7222319 | Timing analysis method and apparatus | — | 2007-05-22 |
| 7197728 | Method for setting design margin for LSI | — | 2007-03-27 |
| 6869808 | Method for evaluating property of integrated circuitry | Satoshi Ishikura | 2005-03-22 |
| 6795802 | Apparatus and method for calculating temporal deterioration margin amount of LSI, and LSI inspection method | Yoshiyuki Kawakami, Nobufusa Iwanishi | 2004-09-21 |
| 6278964 | Hot carrier effect simulation for integrated circuits | Jingkun Fang, Lifeng Wu, Yoshiyuki Kawakami, Nobufusa Iwanishi, Alvin Chen +4 more | 2001-08-21 |
| 6219630 | Apparatus and method for extracting circuit, system and method for generating information for simulation, and netlist | Takuya Umeda, Satoshi Ishikura | 2001-04-17 |
| 5974247 | Apparatus and method of LSI timing degradation simulation | — | 1999-10-26 |
| 5661413 | Processor utilizing a low voltage data circuit and a high voltage controller | Yasuhiro Tomita, Toshiyuki Shono | 1997-08-26 |
| 5475825 | Semiconductor device having combined fully associative memories | Seiji Yamaguchi | 1995-12-12 |
| 5463751 | Memory device having address translator and comparator for comparing memory cell array outputs | Seiji Yamaguchi | 1995-10-31 |