Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System and method for reducing a ground bounce during write by selectively delaying address and data lines with different multiple predetermined amount of delay

System and method for reducing a ground bounce during write by selectively delaying address and data lines with different multiple predetermined amount of delay

US Patent 6760855 · Granted Jul 6, 2004

Estimated economic value: $3,832,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Computational array microprocessor system using non-consecutive data formatting2025
Electronic assembly2024
Computational array microprocessor system using non-consecutive data formatting2023
Dynamic random access memory (DRAM) bandwidth increase without per pin bandwidth2022
Scalable matrix node engine with configurable data formats2022
Computational array microprocessor system using non-consecutive data formatting2021
Systems and methods for converting a matrix input to a vectorized input for a ma2020
Sidecar SRAM for high granularity in floor plan aspect ratio2017
Temperature throttling mechanism for DDR3 memory2015
Memory diagnostics system and method with hardware-based read/write patterns2013
Data processing interface device2013
Method and apparatus for addressing and improving holds in logic networks2013