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Home › Method for reducing stored patterns for IC test by embedding built-in-self-test circuitry for chip logic into a scan test access port

Method for reducing stored patterns for IC test by embedding built-in-self-test circuitry for chip logic into a scan test access port

US Patent 6715105 · Granted Mar 30, 2004

Estimated economic value: $6,543,000 ⓘ

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