Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Internal bus termination technique for integrated circuits with local process/voltage/temperature compensation

Internal bus termination technique for integrated circuits with local process/voltage/temperature compensation

US Patent 6714039 · Granted Mar 30, 2004

Estimated economic value: $6,543,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Transition-based, nonlinear equalization for optical transmission2023
Low power parallelization to multiple output bus widths2017
Continuous tuning of preamble release timing in a double data-rate memory device2015
System and method for high speed data parallelization for an N-phase receiver2014
Communication assets survey and mapping tool with data export feature2014
Communication assets survey and mapping tool with add/edit feature2014
Interfaces, circuits, and methods for communicating with a double data rate memo2012
Communication assets survey and mapping tool2011
Bias circuit for common-mode and semiconductor process voltage and temperature o2011
Identification of board connections for differential receivers2010
Apparatus and method for generating a constant logical value in an integrated ci2010
High-speed receiver assembly2009