Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Continuous tuning of preamble release timing in a double data-rate memory device interface

Continuous tuning of preamble release timing in a double data-rate memory device interface

US Patent 9190129 · Granted Nov 17, 2015

Estimated economic value: $18,907,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Write level training using dual frequencies in a double data-rate memory device 2015
Communication assets survey and mapping tool with data export feature2014
Communication assets survey and mapping tool with add/edit feature2014
Circuits and methods for reducing noise in the power supply of circuits coupled 2012
Interfaces, circuits, and methods for communicating with a double data rate memo2012
Interfaces, circuits, and methods for communicating with a double data rate memo2012
Communication assets survey and mapping tool2011
Method and apparatus for an embedded time domain reflectometry test2009
Method and apparatus for an embedded time domain reflectometry test2009
Hybrid binary/thermometer code for controlled-voltage integrated circuit output 2008
Hybrid binary/thermometer code for controlled-voltage integrated circuit output 2008
System and method for matching data and clock signal delays to improve setup and2007