Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Fast re-synchronization of independent domain clocks after powerdown to enable fast system start-up

Fast re-synchronization of independent domain clocks after powerdown to enable fast system start-up

US Patent 6662305 · Granted Dec 9, 2003

Estimated economic value: $40,688,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Transceiver clock architecture with transmit PLL and receive slave delay lines2016
Random number generator2013
Method and apparatus for interfacing with heterogeneous dual in-line memory modu2013
Optimizing the size of memory devices used for error correction code storage2013
Bus frequency adjustment circuitry for use in a dynamic random access memory dev2013
Optimizing the size of memory devices used for error correction code storage2012
Spread spectrum clock generator2011
Nibble de-skew method, apparatus, and system2011
Synchronous frequency synthesizer2010
Extended synchronized clock2010
Signal drive de-emphasis control for serial bus2009
DC-to-DC voltage converter2009