Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System for measuring phase error between two clocks by using a plurality of phase latches with different respective delays

System for measuring phase error between two clocks by using a plurality of phase latches with different respective delays

US Patent 6636979 · Granted Oct 21, 2003

Estimated economic value: $9,375,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Delay-locked loop with built-in self-test of phase margin2006
Delay-locked loop with built-in self-test of phase margin2006
Delay-locked loop with built-in self-test of phase margin2006
Phase-locked loop with built-in self-test of phase margin and loop gain2001
Phase-locked loop with built-in self-test of phase margin and loop gain2001