Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for a byte lane selectable performance monitor bus

Method and apparatus for a byte lane selectable performance monitor bus

US Patent 6629170 · Granted Sep 30, 2003

Estimated economic value: $10,221,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Network health monitor within a coarse grained reconfigurable architecture proce2025
Handling interrupts from a virtual function in a system with a reconfigurable pr2025
Method for migrating CPU state from an inoperable core to a spare core2025
Peer-to-peer route through in a reconfigurable computing system2025
Scannable memory array and a method for scanning memory2025
Providing deterministic frequency and voltage enhancements for a processor2025
Non-uniform memory interleaving processor2024
Non-uniform memory interleave method2024
Proxy-based instruction throttling control2024
Current prediction-based instruction throttling control2024
Method for migrating CPU state from an inoperable core to a spare core2023
Current prediction-based instruction throttling control2023