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Home › SEMICONDUCTOR DEVICE INCLUDING BUILT-IN REDUNDANCY ANALYSIS CIRCUIT FOR SIMULTANEOUSLY TESTING AND ANALYZING FAILURE OF A PLURALITY OF MEMORIES AND METHOD FOR ANALYZING THE FAILURE OF THE PLURALITY OF MEMORIES

SEMICONDUCTOR DEVICE INCLUDING BUILT-IN REDUNDANCY ANALYSIS CIRCUIT FOR SIMULTANEOUSLY TESTING AND ANALYZING FAILURE OF A PLURALITY OF MEMORIES AND METHOD FOR ANALYZING THE FAILURE OF THE PLURALITY OF MEMORIES

US Patent 6603691 · Granted Aug 5, 2003

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