Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › High speed readout architecture for analog storage arrays

High speed readout architecture for analog storage arrays

US Patent 6366320 · Granted Apr 2, 2002

Estimated economic value: $46,572,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Integrated inductor structure and method of fabrication2015
System and method for reducing voltage drops in integrated circuits2014
Flat wire shielded pair and cable2013
Single-ended sense amplifier with sample-and-hold reference2012
Block redundancy implementation in hierarchical rams2011
Single-poly non-volatile memory cell2011
Dense read-only memory2010
Memory row and column redundancy2010
Hybrid DRAM2010
DRAM architecture2010
RAM with trim capacitors2010
DRAM with reduced power consumption2009