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Home › Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure

Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure

US Patent 6356482 · Granted Mar 12, 2002

Estimated economic value: $4,949,000 ⓘ

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