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Home › Process for the fabrication of an integrated circuit comprising MOS transistors for low voltage, EPROM cells and MOS transistors for high voltage

Process for the fabrication of an integrated circuit comprising MOS transistors for low voltage, EPROM cells and MOS transistors for high voltage

US Patent 6319780 · Granted Nov 20, 2001

Estimated economic value: $13,834,000 ⓘ

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