Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Chip scale package and method for manufacture thereof

Chip scale package and method for manufacture thereof

US Patent 6284566 · Granted Sep 4, 2001

Estimated economic value: $14,434,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Overlapping die stacks for NAND package architecture2025
Surface mount device bonded to an inner layer of a multi-layer substrate2025
Substrates for semiconductor packages, including hybrid substrates for decouplin2025
Systems and methods for reducing the size of a semiconductor assembly2024
Integrated circuit wire bonded to a multi-layer substrate having an open area th2024
Overlapping die stacks for nand package architecture2024
Substrates for semiconductor packages, including hybrid substrates for decouplin2024
Surface mount device bonded to an inner layer of a multi-layer substrate2023
Semiconductor devices with multiple substrates and die stacks2023
Substrates for semiconductor packages, including hybrid substrates for decouplin2022
Overlapping die stacks for NAND package architecture2022
Integrated circuit wire bonded to a multi-layer substrate having an open area th2022