Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › High-speed programmable logic architecture having active CMOS device drivers

High-speed programmable logic architecture having active CMOS device drivers

US Patent 6246259 · Granted Jun 12, 2001

Estimated economic value: $135,399,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Serializer circuitry for high-speed serial data transmitters on programmable log2015
Techniques for aligning and reducing skew in serial data signals2015
High speed serial interface2014
Heterogeneous high-speed serial interface system with phase-locked loop architec2014
Heterogeneous high-speed serial interface system with phase-locked loop architec2014
Techniques for providing clock signals in clock networks2013
Serializer circuitry for high-speed serial data transmitters on programmable log2013
Apparatus and methods for serial interfaces with shared datapaths2013
Method and apparatus for standby voltage offset cancellation2012
Serializer circuitry for high-speed serial data transmitters on programmable log2010
Deserializer circuitry for high-speed serial data receivers on programmable logi2010
Apparatus and method for reset distribution2008