Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for implementing a pseudo least recent used (LRU) mechanism in a four-way cache memory within a data processing system

Method for implementing a pseudo least recent used (LRU) mechanism in a four-way cache memory within a data processing system

US Patent 6240489 · Granted May 29, 2001

Estimated economic value: $28,465,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Composing music using foresight and planning2018
Composing music using foresight and planning2017
Test structure and methodology for three-dimensional semiconductor structures2014
Test structure and methodology for three-dimensional semiconductor structures2012
Structure for reduced area active above-ground and below-supply noise suppressio2012
Structure for automated transistor tuning in an integrated circuit design2011
Structure for a configurable low power high fan-in multiplexer2010
Transmission gate multiplexer2009
Techniques for reducing power requirements of an integrated circuit2009
Pseudo-LRU virtual counter for a locking cache2009
Reduced area active above-ground and below-supply noise suppression circuits2009
Method and apparatus for a configurable low power high fan-in multiplexer2008