Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Process for forming metal interconnects with reduced or eliminated metal recess in vias

Process for forming metal interconnects with reduced or eliminated metal recess in vias

US Patent 6228757 · Granted May 8, 2001

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Fuse-based logic repair2020
Reducing or avoiding mechanical stress in static random access memory (SRAM) str2019
System and method of varying gate lengths of multiple cores2016
Semiconductor device having high mobility channel2016
System and method of varying gate lengths of multiple cores2015
Electrostatic discharge (ESD) protection device for use with multiple I/O standa2012
Electrostatic discharge (ESD) protection device for use with multiple I/O standa2008
Techniques for monitoring and replacing circuits to maintain high performance2007
Integrated circuits with temperature-change and threshold-voltage drift compensa2005
Optimized gate implants for reducing dopant effects during gate etching2004
Etch process that resists notching at electrode bottom2004
Process to control etch profiles in dual-implanted silicon films2003