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Home › Method of extracting 3-D capacitance and inductance parasitics in sub-micron VLSI chip designs using pattern recognition and parameterization

Method of extracting 3-D capacitance and inductance parasitics in sub-micron VLSI chip designs using pattern recognition and parameterization

US Patent 6175947 · Granted Jan 16, 2001

Estimated economic value: $36,198,000 ⓘ

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