Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Low power clock buffer having a reduced, clocked, pull-down transistor

Low power clock buffer having a reduced, clocked, pull-down transistor

US Patent 6124737 · Granted Sep 26, 2000

Estimated economic value: $171,565,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Delivery of foveated rendering streams for media content delivery2025
User authentication based on wireless signal detection in a head mounted device2025
Content personalization based on reinforcement learning2025
Low standby leakage implementation for static random access memory2024
System and method for network initiated embedded subscriber identity module prof2023
Endpoint computing device multi-network slice utilization system2023
Predictive scanning and handover2023
Method and apparatus for intelligent scheduling of network evaluation in wireles2023
Learning based wireless performance adjustment for mobile information handling s2022
Method and apparatus for wireless signal based location security system2022
System and method for optimizing layer three link aggregation in a mesh network2022
Systems and methods of transmitting data over a communication network using qual2022