Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methods and apparatus for a memory that supports a variable number of bytes per logical cell and a variable number of cells

Methods and apparatus for a memory that supports a variable number of bytes per logical cell and a variable number of cells

US Patent 6122717 · Granted Sep 19, 2000

Estimated economic value: $197,268,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Systems, devices, and methods for interactions with an account2021
Systems and methods for delivery techniques of contextualized services on mobile2017
Multi-queue address generator for start and end addresses in a multi-queue first2012
Serial buffer supporting virtual queue to physical memory mapping2011
Multiple counters to relieve flag restriction in a multi-queue first-in first-ou2011
Multi-function queue to support data offload, protocol translation and pass-thro2010
Partial packet write and write data filtering in a multi-queue first-in first-ou2010
Output drive circuit that accommodates variable supply voltages2009
High-speed, low-power level shifter for mixed signal-level environments2009
Mark/re-read and mark/re-write operations in a multi-queue first-in first-out me2009
Multi-queue FIFO memory devices that support a backed-off standard mode of opera2008
Status bus accessing only available quadrants during loop mode operation in a mu2007