Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and circuit for detecting a spurious lock signal from a lock detect circuit

Method and circuit for detecting a spurious lock signal from a lock detect circuit

US Patent 6115438 · Granted Sep 5, 2000

Estimated economic value: $60,044,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

High voltage protection circuit for improved oxide reliability2003
Shared 5 volt tolerant ESD protection circuit for low voltage CMOS process2003
Voltage level shifter with testable cascode devices2002
Digital phase lock loop2002
Digital phase lock loop2002
Shared 5 volt tolerant ESD protection circuit for low voltage CMOS process2002
NMOS triggered NMOS ESD protection circuit using low voltage NMOS transistors2001
Method of designing fail-safe CMOS I/O buffers whose external nodes accept volta2001
Testability circuit for cascode circuits used for high voltage interface2001
CMOS triggered NMOS ESD protection circuit2000
Free running digital phase lock loop2000
Lateral SCR structure for ESD protection in trench isolated technologies2000