Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Stress relief matrix for integrated circuit packaging

Stress relief matrix for integrated circuit packaging

US Patent 6096578 · Granted Aug 1, 2000

Estimated economic value: $50,499,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Component specifying and selection apparatus and method using intelligent graphi2019
Component specifying and selection apparatus and method using intelligent graphi2015
Semiconductor device protective overcoat with enhanced adhesion to polymeric mat2004
Wafer-scale assembly of chip-size packages2004
Wafer-scale assembly of chip-size packages2004
Semiconductor device protective overcoat with enhanced adhesion to polymeric mat2003
Ball grid assembly with solder columns2003
Wafer-scale assembly of chip-size packages2002
Ball grid assembly with solder columns2001
System for positioning a carrier relative to a travel path2001
System for applying a rotary force to strips of varying widths2001
Radiant chamber for simultaneous rapid die attach and lead frame embed for ceram2001