Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Overlay measurement improvement between damascene metal interconnections

Overlay measurement improvement between damascene metal interconnections

US Patent 6093640 · Granted Jul 25, 2000

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method for improving interlevel dielectric gap filling over semiconductor struct2006
Single polysilicon process for DRAM2006
Single poly-si process for DRAM by deep N-well (NW) plate2006
Single poly-Si process for DRAM by deep N well (NW) plate2004
Method for forming high purity silicon oxide field oxide isolation region2004
Method for making closely spaced capacitors with reduced parasitic capacitance o2003
Keyhole at the top metal level prefilled with photoresist to prevent passivation2003
Method for forming a metal gate integrated with a source and drain salicide proc2003
Process for making embedded DRAM circuits having capacitor under bit-line (CUB)2002
Method for making borderless contacts to active device regions and overlaying sh2002
Method for making cost-effective embedded DRAM structures compatible with logic 2002
Technology for high performance buried contact and tungsten polycide gate integr2002