Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Synchronous DRAM cache using write signal to determine single or burst write

Synchronous DRAM cache using write signal to determine single or burst write

US Patent 5953739 · Granted Sep 14, 1999

Estimated economic value: $16,100,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Hybrid MRAM array structure and operation2013
Hybrid MRAM array structure and operation2012
Stacked memory cell structure and method of forming such a structure2011
Hybrid MRAM array structure and operation2010
Method and apparatus for testing a memory device with compressed data using a si2009
Stacked columnar 1T-nMTj MRAM structure and its method of formation and operatio2008
Magnetic tunneling junction antifuse device2008
Stacked columnar 1T-nMTJ MRAM structure and its method of formation and operatio2008
Stacked 1T-nmemory cell structure2008
Stacked 1T-nMTJ MRAM structure2008
Columnar 1T-N memory cell structure2007
Magnetic tunneling junction antifuse device2007