Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Redundancy architecture and method for block write access cycles permitting defective memory line replacement

Redundancy architecture and method for block write access cycles permitting defective memory line replacement

US Patent 5901093 · Granted May 4, 1999

Estimated economic value: $26,914,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Read only memory (ROM) with redundancy2016
Embedded photon emission calibration (EPEC)2015
Apparatuses and methods for capturing data in a memory2014
Read only memory (ROM) with redundancy2014
Circuits and methods for providing refresh addresses and alternate refresh addre2014
Reduced-delay clocked logic2010
Method for improved triggering and oscillation suppression of ESD clamping devic2010
Apparatus and method for improved triggering and oscillation suppression of ESD 2008
Apparatus and method for dynamically controlling data transfer in memory device2007
Method for guaranteeing a minimum data strobe valid window and a minimum data va2004
Method for testing and guaranteeing that skew between two signals meets predeter2003
Multiple memory bank command for synchronous DRAMs2002