Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Cache coherence protocol for reducing the effects of false sharing in non-bus-based shared-memory multiprocessors

Cache coherence protocol for reducing the effects of false sharing in non-bus-based shared-memory multiprocessors

US Patent 5822763 · Granted Oct 13, 1998

Estimated economic value: $13,371,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Operating method and circuit for low density parity check (LDPC) decoder2012
Multi-mode multi-parallelism data exchange method and device thereof2010
Hardware-assisted method for scheduling threads using data cache locality2005
Method and system for dynamically changing page types in unified scalable shared2002
Method for providing virtual atomicity in multi processor environment having acc2001
Method for providing virtual atomicity in multi processor environment having acc2001
Hierarchical bus simple COMA architecture for shared memory multiprocessors havi2000
Hierarchical bus simple COMA architecture for shared memory multiprocessors havi2000
Cache coherence for lazy entry consistency in lockup-free caches2000
Cache coherence for lazy entry consistency in lockup-free caches2000
Home node migration for distributed shared memory systems1999
Efficient method for providing fault tolerance against double device failures in1999