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Operating method and circuit for low density parity check (LDPC) decoder |
Chih-Hao Liu, Yen-Chin Liao, Chen-Yi Lee, Hsie-Chia Chang |
2012-01-31 |
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Multi-mode multi-parallelism data exchange method and device thereof |
Chih-Hao Liu, Chien-Ching Lin, Chen-Yi Lee, Hsie-Chia Chang |
2010-05-18 |
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Method for providing virtual atomicity in multi processor environment having access to multilevel caches |
Sandra Johnson Baylor |
2001-01-16 |
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Hierarchical bus simple COMA architecture for shared memory multiprocessors having a bus directly interconnecting caches between nodes |
Sandra Johnson Baylor |
2000-11-14 |
| 6094709 |
Cache coherence for lazy entry consistency in lockup-free caches |
Sandra Johnson Baylor, Anthony Simon Bolmarcich, Ching-Farn E. Wu |
2000-07-25 |
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Cache coherence protocol for reducing the effects of false sharing in non-bus-based shared-memory multiprocessors |
Sandra Johnson Baylor |
1998-10-13 |
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Invalidation bus optimization for multiprocessors using directory-based cache coherence protocols in which an address of a line to be modified is placed on the invalidation bus simultaneously with sending a modify request to the directory |
Sandra Johnson Baylor |
1998-07-07 |
| 5313649 |
Switch queue structure for one-network parallel processor systems |
Rory Jackson |
1994-05-17 |
| 5287491 |
Network rearrangement method and system |
— |
1994-02-15 |
| 5046000 |
Single-FIFO high speed combining switch |
— |
1991-09-03 |
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Programmable variable-cycle clock circuit for skew-tolerant array processor architecture |
Hungwen Li |
1989-07-25 |
