Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix

Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix

US Patent 5764078 · Granted Jun 9, 1998

Estimated economic value: $2,721,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Efficiently transmitting bulk data over a mobile network2017
Clock distribution chip2012
Clock distribution chip2012
Flexible memory architectures for programmable logic devices2011
Programmable logic device with a multi-data rate SDRAM interface2010
Programmable logic devices with custom identification systems and methods2010
Programmable logic device with multiple slice types2010
Dual-slice architectures for programmable logic devices2010
Clock distribution chip for generating both zero-delay and non-zero-delay clock 2010
Area efficient routing architectures for programmable logic devices2009
Logic block control architectures for programmable logic devices2009
Programmable logic device with enhanced logic block architecture2009