Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for creating a high speed scan-interconnected set of flip-flop elements in an integrated circuit to enable faster scan-based testing

Method for creating a high speed scan-interconnected set of flip-flop elements in an integrated circuit to enable faster scan-based testing

US Patent 5717700 · Granted Feb 10, 1998

Estimated economic value: $14,504,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Battery enhancing vehicle internal temperature monitoring device2025
Method and system for insertion of cybersecurity and hardware assurance instrume2025
Seebeck effect renewable energy arrangement2024
Method, system, and apparatus for security assurance, protection, monitoring and2024
Method, system, and apparatus for security assurance, protection, monitoring and2023
Using embedded time-varying code generator to provide secure access to embedded 2023
Method, system and apparatus for security assurance, protection, monitoring and 2023
Using embedded time-varying code generator to provide secure access to embedded 2022
Method, system, and apparatus for verification of operation using GPS receiver i2022
Method and system for selection of location for placement of trojans, triggers a2021
Method and system for selection of location for placement of trojans, triggers a2021
Using embedded time-varying code generator to provide secure access to embedded 2020